High Voltage Ring Pump

ABSTRACT

A multi-stage device for boosting an input voltage is discussed. Each stage of the device comprises a stage of a ring oscillator and a charge pump. An oscillating signal, generated by the ring oscillator within the device, drives the charge pump in each stage of the device. The charge pumps of the stages are serially connected. A final stage of the multi-stage device is adapted to provide voltage to a load circuit. The multi-stage device is applicable for generation of different bias voltages from one or more source voltages.

FIELD

The disclosure relates generally to electronic integrated circuits. More specifically, it relates to a high voltage ring pump.

BACKGROUND

Given the number and complexity of components on any integrated circuit (IC), it is rarely the case that all of these components can function optimally using a single voltage supply. However, the use of many different voltage supplies, whether external or internal to the IC, may be undesirable. Additional external voltage supplies required in order for the IC to operate correctly may be inconvenient for the user of the IC. Additional voltage supplies internal to the IC may violate area requirements of a chip.

Consequently, a common method by which to generate the different voltage supplies required by each of the components is to build auxiliary circuitry onto the IC that generates the different voltages. A charge pump is one such auxiliary circuit that functions as a DC to DC converter. The charge pump takes in an input voltage and generates an output voltage that is either higher in magnitude or lower in magnitude than the input voltage, depending on the application required. Charge pumps generally utilize an energy storage element to generate the output voltage.

SUMMARY

According to a first aspect of the disclosure, a circuital arrangement adapted to provide voltage to a load circuit is provided, comprising a plurality of charge pumps, wherein each charge pump comprises an inverter stage and a voltage boosting stage, the circuital arrangement thus comprising: a plurality of inverter stages ring connected therebetween; and a plurality of voltage boosting stages serially connected therebetween.

According to a second aspect of the disclosure, a charge pump element is provided, comprising: an initial inverter, wherein an input voltage to the initial inverter is inverted to obtain a complementary output voltage; at least one pump block, wherein an output voltage of a particular pump block in the at least one pump block is larger in magnitude than an input voltage to the particular pump block in the at least one pump block; and a driving circuit connected with the initial inverter on one end and the at least one pump block on another end, wherein the driving circuit generates a first voltage and a second voltage based on the input voltage to the initial inverter, and wherein each of the first and second voltages are adapted to be applied to the at least one pump block.

According to a third aspect of the disclosure, a circuital arrangement adapted to provide an output voltage to a load circuit is provided, comprising: a plurality of inverter stages ring connected therebetween; and a plurality of voltage boosting stages serially connected therebetween, wherein: each voltage boosting stage is coupled with one inverter stage in the plurality of inverter stages, an output of a voltage boosting stage in the plurality of voltage boosting stages is higher in magnitude than an output of a previous voltage boosting stage in the plurality of voltage boosting stages, and a last voltage boosting stage in the plurality of voltage boosting stages is adapted to provide the output voltage to the load circuit.

According to a fourth aspect of the disclosure, a method for boosting voltage is provided, comprising: generating a first oscillating signal; generating a second oscillating signal complementary to the first oscillating signal; and accumulating voltage based on the first oscillating signal and the second oscillating signal.

Further embodiments are provided in the specification, drawings, and claims of the present application.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of example embodiments, serve to explain the principles and implementations of the disclosure.

FIG. 1 shows an exemplary diagram of an individual full-wave pump element and illustrates input terminals and output terminals of the individual full-wave pump element.

FIG. 2 shows a schematic of a ring pump according to an embodiment of the disclosure.

FIG. 3A shows a block diagram that illustrates components of the individual full-wave pump element according to an embodiment of the disclosure.

FIG. 3B shows a possible arrangement of components that implements the individual full-wave pump element shown in FIG. 3A.

FIG. 4 shows a schematic of the ring pump according to another embodiment in the disclosure.

FIG. 5 shows a top view of a circuit layout of an individual full-wave pump element.

FIG. 6 shows input voltages of a first full-wave pump element and a last full-wave pump element of the ring pump shown in FIG. 4.

FIG. 7 shows an output voltage of the ring pump in FIG. 4 as a function of time and a load circuit from which the output voltage is measured.

FIG. 8A shows an output voltage of DC blocking capacitors as a function of time without taking into account parasitic elements.

FIG. 8B shows an output voltage of a multiple-stage ring pump as a function of time without taking into account parasitic elements.

FIG. 8C shows the output voltage of the DC blocking capacitors as a function of time while taking into account parasitic elements.

FIG. 8D shows the output voltage of the multiple-stage ring pump as a function of time while taking into account parasitic elements.

FIG. 9 shows a chip layout that includes different embodiments of ring pumps.

FIG. 10 shows output voltages of the various ring pumps in FIG. 9 as a function of time.

FIG. 11 shows an exemplary chip layout of a ring pump.

FIGS. 12A-12C show graphs of output voltages of different embodiments of the ring pump as a function of output current of the ring pump.

DETAILED DESCRIPTION

Throughout the present disclosure, a charge pump will sometimes be referred to as a “pump”. According to several embodiments of the present disclosure, full-wave pumps, also referred to as FWPumps, are described. An FWPump is a charge pump comprising a full-wave bridge rectifier. Additionally, the present disclosure will discuss, with reference to the accompanying figures, operation and embodiments of a ring pump. The ring pump comprises a plurality of charge pumps and is adapted to provide an output voltage to a load circuit. In accordance with several embodiments of the present disclosure, a ring pump comprises an odd plurality of FWPumps connected in a ring connection. Alternatively, a ring pump may comprise an even plurality of FWPumps and an odd number of inverters. Such an inverter can precede or follow an FWPump or be connected between two FWPumps. Consequently, a stage of the ring pump, as used throughout the present disclosure, can comprise either an FWPump or simply an inverter.

FIG. 1 shows an exemplary diagram of an individual FWPump (100) element. The FWPump (100) is a four terminal device with two inputs and two outputs. In particular, the FWPump (100) comprises an IN terminal (105) that takes in a first input voltage V_(IN) (125), an OUT terminal (110) that sends out a first output voltage V_(OUT) (130), a NEG terminal (115) that takes in a second input voltage V_(NEG) (140), and a POS terminal (120) that sends out a second output voltage V_(POS) (145). The four terminals (105, 110, 115, 120) of the FWPump (100) will be discussed in detail in relation to FIGS. 2, 3A, and 3B.

FIG. 2 shows an embodiment of a ring pump. In particular, FIG. 2 shows an exemplary three-stage ring pump. The three-stage ring pump comprises a first FWPump (200), a second FWPump (205), and a third FWPump (210). Each FWPump (200, 205, 210) comprises an inverter stage and a voltage boosting stage, the implementations of which are not shown directly in FIG. 2 and will be discussed in detail in relation to FIGS. 3A and 3B. As shown in FIG. 2, the ring pump thus comprises a plurality of ring connected inverter stages and a plurality of serially connected voltage boosting stages.

By way of example and not of limitation, assume that a positive oscillator supply voltage V_(DD)=+2 V and a negative oscillator supply voltage V_(SS)=−1 V are applied to inverters (not shown) in the FWPumps (200, 205, 210). The inverters are thus adapted to have a high voltage state of +2 V and a low voltage state of −1 V in this example. Consequently, voltage swing is given by V_(DD)−V_(SS)=+3 V. It should be noted that the terms “positive” and “negative” are not used to designate absolute polarity but are rather used to designate a relationship between V_(DD) and V_(SS), specifically that V_(DD)>V_(SS). For instance, V_(SS) can be 0 V, which is not a negative voltage.

The inverter stage in each FWPump (200, 205, 210) is performed as follows. Consider a first inverter stage voltage V_(IS1) (222) that is initially, and arbitrarily, set to V_(IS1)=+2 V; the voltage V_(IS1) (222) is the voltage applied to the first FWPump's IN terminal (220). The inverter stage of the first FWPump (200) will invert voltage state of the voltage V_(IS1) (222) to a complementary voltage state and output the resulting voltage as a second inverter stage voltage V_(IS2) (226). Consequently, in the present example, the voltage V_(IS2) (226) is V_(IS2)=−1 V. The first FWPump's (200) OUT terminal (224) serially connects to the second FWPump's (205) IN terminal (228) and thus the input voltage applied to the second FWPump's (205) IN terminal (228) is the voltage V_(IS2) (226).

The inverter stage of the second FWPump (205) inverts voltage state of the voltage V_(IS2) (226) and outputs the resulting voltage as a third inverter stage voltage V_(IS3) (232). In the present example, the voltage V_(IS3) (232) is V_(IS3)=+2 V. The second FWPump's (205) OUT terminal (230) serially connects to the third FWPump's (210) IN terminal (234) and thus the input voltage applied to the third FWPump's IN terminal (234) is the voltage V_(IS3) (232).

The inverter stage of the third FWPump (210) inverts voltage state of the voltage V_(IS3) (232). As seen in FIG. 2, the third FWPump's (210) OUT terminal (236) serially connects to the first FWPump's (200) IN terminal (220). Therefore, the voltage V_(IS1) (222) is V_(IS1)=−1 V, which is opposite in voltage state to the initial value of V_(IS1) (222).

The inverter stages of the three FWPumps (200, 205, 210) of FIG. 2 are connected in a ring structure. The ring connection formed by the inverter stage of each individual FWPump (100 in FIG. 1) is henceforth referred to as an inverter ring. Although a three-stage ring pump is shown in FIG. 2, the skilled person in the art would have no trouble increasing the number of stages in the ring pump.

With further reference to FIG. 2, in addition to the inverter stage, each FWPump (200, 205, 210) further comprises the voltage boosting stage, where (as will be shown with reference to FIGS. 3A and 3B) the voltage boosting stage is a function of (depends on) voltages of the inverter stage. Consider an initial voltage V₀ (250) that is of an arbitrary value and is connected to the first FWPump's (200) NEG terminal (252). The voltage boosting stage of the first FWPump (200) will take the initial voltage V₀ (250) and increase the voltage (in magnitude). The resulting voltage is a first voltage boosting stage voltage V₁ (256), where |V₁|>|V₀|. The voltage V₁ (256) is the voltage at the first FWPump's (200) POS terminal (254).

Since the first FWPump's (200) POS terminal (254) is serially connected to the second FWPump's (205) NEG terminal (258), the voltage V₁ (256) is the voltage input into the second FWPump's (205) NEG terminal (258). The voltage boosting stage of the second FWPump (205) will take the voltage V₁ (256) and increase the voltage (in magnitude). Thus, the resulting voltage is a second voltage boosting stage voltage V₂ (262), where |V₂|>|V₁|.

The voltage V₂ (262) is the voltage at the second FWPump's (205) POS terminal (260) and the third FWPump's (210) NEG terminal (264). The voltage boosting stage of the third FWPump (210) increases the magnitude of the voltage V₂ (262). The resulting voltage is a ring pump output voltage V_(ring3) (270), where |V_(ring3)|>|V₂|. The voltage V_(ring3) (270) is the voltage at the third FWPump's (210) POS terminal (266). Since the embodiment in FIG. 2 only has three stages, the voltage V_(ring3) (270) is the output voltage of the ring pump, which is the voltage applied to an arbitrary load circuit (280).

In several embodiments of the present disclosure, the voltage boosting stage of each FWPump increases voltage in a positive direction. In relation to the ring pump shown in FIG. 2, the relative values of the voltages are given by V_(ring3)>V₂>V₁>V₀.

Specifically, the first FWPump (200) in FIG. 2 sits on a pedestal voltage given by the initial voltage V₀ (250) and generates the first voltage boosting stage voltage V₁ (256). The first voltage V₁ (256) is the initial voltage V₀ (250) boosted by the voltage swing V_(DD)−V_(SS). Consequently, the first voltage V₁ (256) is given by V₁=V₀+(V_(DD)−V_(SS)).

Similarly, the second FWPump (205) in FIG. 2 sits on a pedestal voltage given by the first voltage V₁ (256) and generates the second voltage boosting stage voltage V₂ (262). The second voltage V₂ (262) is the first voltage V₁ (256) boosted by the voltage swing V_(DD)−V_(SS). Therefore, the second voltage V₂ (262) is given by V₂=(V_(DD)−V_(SS))=V₀+2(V_(DD)−V_(SS)).

Finally, the third FWPump (210) in FIG. 2 sits on a pedestal voltage given by the second voltage V₂ (262) and generates the ring pump output voltage V_(ring3) (270). The output voltage V_(ring3) (270) is boosted by the voltage swing and thus V_(ring3)=V₂+(V_(DD)−V_(SS))=V₁+2(V_(DD)−V_(SS))=V₀+3(V_(DD)−V_(SS)).

As a numerical example, consider that V_(DD)=+2 V, V_(SS)=−1 V, and V₀=0 V. The three voltage boosting stage voltages (256, 262, 270) are V₁=3 V, V₂=6 V, and V_(ring3)=9 V. Taking into consideration losses associated with each of the components used to implement an FWPump (200, 205, 210), each of the voltages V₁ (256), V₂ (262), and V_(ring3) (270) will generally be lower than those values given above.

In another embodiment of the present disclosure, the voltage boosting stage of each FWPump increases voltage in a negative direction. Using the ring pump in FIG. 2 as an example, in order for the voltage boosting stage of each FWPump (200, 205, 210) to increase voltage in a negative direction, the NEG terminal (252, 258, 264) and the POS terminal (254, 260, 266) of each FWPump (200, 205, 210) are flipped for each FWPump (200, 205, 210). The relative values of the voltages in this case are given by V₀>V₁>V₂>V_(ring3). Equivalently, to increase voltage in the negative direction, the POS terminals (254, 260, 266) and NEG terminals (252, 258, 264) may remain as they appear in FIG. 2, but the initial voltage V₀ (250) would instead be tied to the third FWPump's POS terminal (266) while the load circuit (280) would be tied to the first FWPump's NEG terminal (252).

The actual operation of the ring pump in FIG. 2 will become clear when the ring pump in FIG. 2 is explained in relation to FIGS. 3A and 3B.

FIG. 3A shows a block diagram that illustrates a possible implementation of the FWPump (100) element shown in FIG. 1, according to an embodiment of the present disclosure. Terminals IN (105), OUT (110), NEG (115), and POS (120) shown in FIG. 3A refer to the same terminals (105, 110, 115, 120) as those shown in FIG. 1. Similarly, voltages V_(IN) (125), V_(OUT) (130), V_(NEG) (140), and V_(POS) (145) shown in FIG. 3A refer to the same voltages (125, 130, 140, 145) as those shown in FIG. 1. Consequently, the same reference numerals are used to refer to the terminals (105, 110, 115, 120) and the voltages (125, 130, 140, 145) in both figures.

The FWPump (100) comprises an inverter stage. Operation of the inverter stage is as follows and is made with reference to FIG. 3A. The IN terminal (105) of the FWPump (100) takes as its input the output of a previous FWPump's OUT terminal (not shown in FIG. 3A). The input voltage V_(IN) (125) is sent into a first inverter (305), which inverts the input voltage V_(IN) (125) and sends the resulting output voltage V_(OUT) (130) to a next FWPump (not shown in FIG. 3A) via the OUT terminal (110). The voltage state of the output voltage V_(OUT) (130) is opposite the voltage state of the input voltage V_(IN) (125). Consequently, the first inverter (305) implements the inverter stage of the individual FWPump (100).

The FWPump (100) further comprises a voltage boosting stage. FIG. 3A shows possible components used to implement the voltage boosting stage. All components shown in FIG. 3A, including the first inverter (305) used in the inverter stage of the FWPump (100), are used in the voltage boosting stage. Overall operation of the voltage boosting stage is as follows. The NEG terminal (115) of the FWPump (100) takes as its input the output of the previous FWPump's POS terminal (not shown), which is the voltage V_(NEG) (140) shown in FIG. 3A. After the voltage boosting stage of the FWPump (100) is completed, the FWPump (100) will output the voltage V_(POS) (145) at the POS terminal (120), where |V_(POS)|>|V_(NEG)|.

With continued reference to FIG. 3A, general operation with reference to each component in the voltage boosting stage will now follow. The output voltage V_(OUT) (130) of the first inverter (305) is sent into a second inverter (315) serially connected to the first inverter (305). Voltage state of the second inverter's output voltage V₂ (318) is the same as voltage state of the original input voltage V_(IN) (125). Similarly, the output voltage V_(OUT) (130) of the first inverter (305) is also sent into a third inverter (320), which results in a third inverter's output voltage V₃ (322) with a same voltage state as that of the input voltage V_(IN) (125). The voltage V₃ (322) is the input to a fourth inverter (325). The fourth inverter (325) inverts the voltage V₃ (322) and outputs a fourth inverter's output voltage V₄ (328) with a voltage state opposite that of the voltage V₃ (322) and thus a voltage state opposite that of the original input voltage V_(IN) (125). In summary, if the input voltage V_(IN) (125) is arbitrarily set to the high voltage state, then the voltages V_(IN) (125), V₂ (318), and V₃ (322) are in the high voltage state and the voltages V_(OUT) (130) and V₄ (328) are in the low voltage state.

The outputs of the second inverter (315) and the fourth inverter (325) are applied to a first DC blocking capacitor (330) and a second DC blocking capacitor (335), respectively. The DC blocking capacitors (330, 335) are connected to a full-wave bridge rectifier (385). The full-wave bridge rectifier (385) is connected, in turn, to a reservoir capacitor (370). The FWPump's (100) NEG terminal (115) and POS terminal (120) are directly tied to a circuit comprising the full-wave bridge rectifier (385) and the reservoir capacitor (370). Consequently, the voltage boosting stage of each FWPump (100) is a function of voltages involved in the voltage boosting stage due to connection between the inverter stage of each FWPump (100) to the voltage boosting stage of the FWPump (100) via the first and second DC blocking capacitors (330, 335). Operation of the DC blocking capacitors (330, 335), full-wave bridge rectifier (385), and reservoir capacitor (370) will be discussed in relation to FIG. 3B.

The reservoir capacitor (370) of each FWPump (100) functions as a charge storage device for storing charges generated by the voltage boosting stage of each FWPump (100). It should be noted that although the term “capacitor” is used, the reservoir capacitor (370) need only be any component that has an impedance that is more capacitive than resistive or inductive. In selecting a reservoir capacitor (370), threshold voltage (when using FETs as capacitors) and breakdown voltage are exemplary parameters. A DN FET, as shown in FIGS. 3A and 3B, is only one possible implementation of the reservoir capacitor (370).

The operation of the ring pump with reference to the three-stage ring pump shown in FIG. 2 and the embodiment of the FWPump (100) shown in FIG. 3A will now be described.

Consider, as before, that the inverters have a positive oscillator supply voltage V_(DD)=+2 V and a negative oscillator supply voltage V_(SS)=−1 V. The inverters are adapted to have a high voltage state of +2 V and a low voltage state of −1 V. It should be noted that values used for the supply voltages V_(DD) and V_(SS) can differ from example values given in the present disclosure. Depending on the application, the positive supply voltage V_(DD) could be, for instance, 3.3 V or 2.5 V, while the negative supply voltage V_(SS) could be tied to ground.

Consider a first iteration through the ring pump in FIG. 2 where the first inverter stage voltage V_(IS1) (222) is set to an exemplary value of +2 V. As previously mentioned, the resulting second inverter stage voltage V_(IS2) (226) and third inverter stage voltage V_(IS3) (232) are −1 V and +2 V, respectively. The third inverter stage voltage V_(IS3) (232) is inverted by the third FWPump (210), yielding a voltage of −1 V. Since the third FWPump's (210) OUT terminal (236) serially connects to the first FWPump's (200) IN terminal (220), the −1 V is the value of the first inverter stage voltage V_(IS1) (222). Consequently, in a second iteration through the inverter ring, the resulting inverter stage voltages V_(IS1) (222), V_(IS2) (226), and V_(IS3) (232) are −1 V, +2 V, and −1 V, respectively.

Each inverter stage voltage (222, 226, 232) changes voltage states in the second iteration relative to the corresponding inverter stage voltage (222, 226, 232) in the first iteration. Consequently, each iteration through the inverter stages of each FWPump (200, 205, 210) will reverse voltage state of the inverter stage voltages (222, 226, 232). The values for the inverter stage voltages (222, 226, 232) will not stabilize as a result of there being an odd number of stages.

As seen in relation to FIG. 3A, the input voltage V_(IN) (125) for the inverter stage of the FWPump (100) is used to drive the voltage boosting stage. The voltage V₂ (318) is applied to the first capacitor (330). The voltage V₄ (322), which is in an opposite voltage state relative to the voltage V₂ (318), is applied to the second capacitor (335).

The input voltage V_(IN) (125) is set to the voltage V_(IS1) (222 in FIG. 2). The voltage V_(IS1) (222 in FIG. 2) reverses voltage state with each iteration through the inverter ring. Consequently, the voltages V₂ (318), V₃ (322), and V₄ (328) also reverse voltage states with each iteration. The reversing of the voltage state for voltages V₂ (318) and V₄ (328) creates the equivalent of an AC signal at the first capacitor (330) and the second capacitor (335), respectively. A first capacitor voltage output V_(P) (332) is the output of the first capacitor (330). A second capacitor voltage output V_(Pb) (338) is the output of the second capacitor (335).

Both the first capacitor (330) and the second capacitor (335) are connected to the full-wave bridge rectifier (385) and thus both voltages V_(P) (332) and V_(Pb) (338) are applied to the full-wave bridge rectifier (385). In a first state, the voltage V_(P) (332) is larger than the voltage V_(Pb) (338). In a second state, the voltage V_(Pb) (338) is larger than the voltage V_(P) (332). It will be shown in relation to FIG. 3B that in both the first state and the second state, the full-wave bridge rectifier (385) will charge up the reservoir capacitor (370). Since the inverter ring of the ring pump prevents the input voltage V_(IN) (125) at the IN terminal (105) of each FWPump (100) from stabilizing, each iteration through the inverter ring will serve to charge up the reservoir capacitor (370).

The reservoir capacitor (370) functions as follows in relation to voltage boosting. The FWPump (100) has the voltage V_(NEG) (140) applied to its NEG terminal (115), where the voltage V_(NEG) (140) is an output voltage of the voltage boosting stage of the previous FWPump (not shown). The voltages V_(P) (332) and V_(Pb) (338) applied to the full-wave bridge rectifier (385) will charge up the reservoir capacitor (370) of the FWPump (100). The voltage V_(NEG) (140) is applied to both the full-wave bridge rectifier (385) and the reservoir capacitor (370). The value of the output voltage V_(POS) (145) of the FWPump (100) is the sum of the input voltage V_(NEG) (140) and a voltage value that quantifies charge stored by the reservoir capacitor (370). Consequently, after the voltage boosting stage of the FWPump (100), the output voltage V_(POS) (145) of the FWPump (100) is greater in magnitude than the input voltage V_(NEG) (140) of the FWPump (100).

With continued reference to FIG. 3A, it should be noted that all components of the individual FWPump (100) to the right of the first inverter (305) aid in buffering the OUT terminal (110) from these other components. Buffering refers to isolation (reduction in coupling) between AC loads and AC signals. Specifically, the inverters (315, 320, 325) buffer the V_(OUT) (130), which oscillates between the supply voltages V_(DD) and V_(SS), from loading as well as from variability in power delivery from the supply voltages V_(DD) and V_(SS). This buffering allows the inverter ring to run at a high and constant speed, without regard to the other activities, specifically the activities of the voltage boosting stage, occurring within the individual FWPump (100). Specifically, without buffering, oscillation frequency of the inverter ring fluctuates due to coupling between the inverter stage and the voltage boosting stage, and fluctuation of the oscillation frequency reduces speed of the inverter ring and voltage output of each FWPump (100) in a ring pump.

The first and second DC blocking capacitors (330, 335) provide DC isolation by preventing DC current from leaking back from the reservoir capacitor (370) to the first and second DC blocking capacitors (330, 335). Specifically, the first and second DC blocking capacitors (330, 335) provide the isolation between the inverter ring, which is associated with lower voltages, and activities of the voltage boosting stage, which can be associated with higher voltages, by preventing DC coupling between the various inverters (305, 315, 320, 325), shown to the left of the capacitors (330, 335), and the full-wave bridge rectifier (385) and the reservoir capacitor (370), shown to the right of the capacitors (330, 335). Consequently, output power of the ring pump would be drawn from the NEG terminal (115) and the POS terminal (120) of each FWPump (100) and little (if any) power would be drawn from the inverters (305, 315, 320, 325) in the inverter stage. Without DC isolation between the inverter and voltage boosting stages, the full-wave bridge rectifier (385) may draw current from the OUT terminal (110), which can affect voltage multiplication obtained through stacking of the voltage boosting stages.

FIG. 3B shows a circuit schematic that illustrates circuit components that may be used to implement each of the blocks in the block diagram on FIG. 3A. The details in the circuit schematic and circuit components are specific to a particular semiconductor process utilized in the present disclosure, but the skilled person can adjust details to fit different semiconductor parameters.

The exemplary process of FIG. 3B includes the following FET types, from which a majority of circuit components are fabricated. By way of example, N-channel FETs include: regular N (“RN”) FETs that have a nominal threshold voltage of 450 mV, high doping N (“HN”) FETs that have a nominal threshold voltage of 700 mV, and depletion mode N (“DN”) FETs that have a threshold voltage below 0 V. Corresponding P-channel FETs include regular P FETs (“RP”) that have a nominal threshold voltage of −400 mV and high doping FETs (“HP”) that have a nominal threshold voltage of −600 mV. In another embodiment of the present disclosure, HN, RN, HP, and RP FETs may have nominal threshold voltages of 800 mV, 300 mV, −800 mV, and −300 mV, respectively. Other FETs, such as an intrinsic N-channel (“IN”) FET can be utilized. The IN FET may have a threshold voltage of approximately 0 V. Additional parameters in selecting a particular FET as the charge storage device include, by way of example and not of limitation, series resistance and density of capacitance of the particular FET.

In the embodiment shown in FIG. 3B, the first inverter (305), the second inverter (315), the third inverter (320), and the fourth inverter (325) are all implemented using HP FETs and HN FETs. The full-wave bridge rectifier (385) is implemented using RP FETs and RN FETs. It should be noted, however, that the full-wave bridge rectifier (385) can also be implemented using diodes as well as various other devices, identifiable by the skilled person in the art, capable of rectifying action. The reservoir capacitor (370) is implemented using a DN FET. Selection of a particular type of N-channel FET and P-channel FET depends primarily on different threshold voltages of each type of FET. Each FET used to implement the inverters (305, 315, 320, 325) is supplied with a positive voltage supply V_(DD) and a negative voltage supply V_(SS).

It is to be understood that MOS transistors are used as switches in this particular embodiment, as seen in the implementation of the various inverters (305, 315, 320, 325) and the full-wave bridge rectifier (385). An alternative embodiment of the ring pump may utilize, for instance, diodes or diode-connected transistors as switches in an implementation of the full-wave bridge rectifier (385). Similarly, it is to be noted again that DN FETs are used as reservoir capacitors (370) in this embodiment. However, any passive element that has an impedance that is more capacitive than inductive or resistive at the frequency of interest may serve as a capacitor in this disclosure.

With continued reference to FIG. 3B, the output of the first capacitor (330) is denoted as node P (340). Node P (340) is connected to the drain of a first PMOS (350) and the drain of a first NMOS (355); node P (340) is also connected to the gate of a second PMOS (360) and the gate of a second NMOS (365). The output of the second capacitor (335) is denoted as node Pb (345). Node Pb (345) is connected to the gate of the first PMOS (350) and the gate of the first NMOS (355); node Pb (345) is also connected to the drain of the second PMOS (360) and the drain of the second NMOS (365). The source of the first PMOS (350) and the source of the second PMOS (360) are connected; both the source of the first PMOS (350) and the source of the second PMOS (360) are tied to the POS terminal (120). The source of the first NMOS (355) and the source of the second NMOS (365) are also connected; both the source of the first NMOS (355) and the source of the second NMOS (365) are tied to the NEG terminal (115). These components and connections are used to implement the embodiment of the full-wave bridge rectifier (385) shown in FIG. 3B.

A simplified description of the operation of the full-wave rectifier circuit (385) is given as follows. Consider a first state when the P node (340) is at a higher voltage than the Pb node (345), the first PMOS (350) and the second NMOS (365) are switched on whereas the first NMOS (355) and the second PMOS (360) are switched off The transistors that are switched on, henceforth referred to as conducting transistors, charge up the reservoir capacitor (370).

Similarly, consider a second state when the Pb node (345) is at a higher voltage than the P node (340), the first NMOS (355) and the second PMOS (360) are switched on whereas the first PMOS (350) and the second NMOS (365) are switched off The conducting transistors again charge up the reservoir capacitor (370). Consequently, the reservoir capacitor (370) is being charged during the times when the P node (340) is at a higher voltage than the Pb node (345), and vice versa.

Rectifying nature of the full-wave bridge rectifier (385) produces unidirectional current flow. In other words, charge is delivered in a direction of a load circuit (such as 280 in FIG. 2) regardless of whether the P node (340) has a higher voltage than the Pb node (345), or vice versa.

Output voltage waveforms from the first state and second state are generally designed to be complementary to each other. In several embodiments of the present disclosure, the complementary voltage waveforms result from utilizing same capacitance values for both capacitors (330, 335) and applying the same two voltages V_(DD) and V_(SS) to both capacitors (330, 335), where inputs to the capacitors (330, 335) are different voltage states selected from two voltage states V_(DD) and V_(SS). Specifically, one capacitor (330, 335) has an applied voltage of V_(DD) when the other capacitor (330, 335) has an applied voltage of V_(SS), and vice versa. Providing such symmetry in the capacitance and voltage values is one method to reduce noise and promote voltage balance in each FWPump.

Consequently, according to many embodiments of the present disclosure, the ring pump accumulates or boosts voltage by generating a first oscillating signal to be applied to one capacitor (330, 335) and a second oscillating signal complementary to the first oscillating signal to be applied to the other capacitor (330, 335). As shown for example in FIGS. 3A and 3B, the second oscillating signal can be generated by inverting the first oscillating signal. The ring pump accumulates or boosts voltage based on the first and second oscillating signals provided to the voltage boosting stages of the FWPumps that form the ring pump.

Voltage across each of the capacitors (330, 335) changes by around the voltage swing |V_(DD)−V_(SS)| between transitions from the high voltage state V_(DD) and the low voltage state V_(SS). Consider a case where the first capacitor (330) transitions from the high voltage state V_(DD) to the low voltage state V_(SS) while the second capacitor (335) transitions from the low voltage state V_(SS) to the high voltage state V_(DD). A first charge pulse of amplitude Q=C(V_(SS)−V_(DD)) passes through the first capacitor (330) and a second charge pulse of amplitude Q=C(V_(DD)−V_(SS)) passes through the second capacitor (335), resulting in a first capacitor current I_(C0) (334) and a second capacitor current I_(C1) (339), respectively. These charge pulses are sent through the full-wave rectifier bridge (385) and into the reservoir capacitor (370).

A low ripple voltage arises from application of the full-wave bridge rectifier (385) and the complementary voltage waveforms of the capacitors (330, 335). Since the voltage waveforms are complementary, the first capacitor current I_(C0) (334) and second capacitor current I_(C1) (339) are equal in magnitude and opposite in sign. Due to the equal magnitude of the currents (334, 339), no net charge comes from the NEG terminal (115) and the POS terminal (120) regardless of whether the P node (340) has a higher voltage than the Pb node (345), or vice versa. Consequently, the reservoir capacitor (370) of the individual FWPump (100) is charged by the voltage boosting stage of the individual FWPump (100) itself, without taking charge from a previous FWPump (not shown) via the NEG terminal (115) or from a subsequent FWPump (not shown) via the POS terminal (120).

Additionally, transition of the voltages (from V_(DD) to V_(SS) and vice versa) through the inverter ring spreads charge transfer events over time from the capacitors (330, 335) to the reservoir capacitor (370). For example, with reference to the three-stage ring pump shown in FIG. 2, the charge transfer events are due to six charge pulses, where one pulse comes from each of the first and second capacitors (330, 335 in FIGS. 3A and 3B) of each of the three FWPumps (200, 205, 210). Alternatively, consider a single charge pump that can supply one single charge pulse that is equal in magnitude to the sum of the six charge pulses. The single large charge transfer event yields high amplitude charge impulses which can produce undesirable noise in the ring pump output voltage V_(ring3) (270) as well as the supply voltages V_(DD) and V_(SS). By spreading the pulses across three stages (or N stages in the general case) and running the stages at a high frequency, the charge transfer events become overlapped and appear nearly DC, as shown, for instance, in output voltage versus time plots in subsequent FIGS. 8B and 8D. The output voltage of the ring pump quantifies the charge transfer events.

In the present embodiment shown in FIG. 3B, the DN FET used to implement the reservoir capacitor (370) in the individual FWPump (100) is generally larger in size than the other transistors, henceforth referred to as active devices, used in the implementation of the ring pump. Note that capacitance of the reservoir capacitor (370) allows current flow toward a load circuit (such as 280 in FIG. 2). To the contrary, parasitic capacitances cause current flow through various conducting paths, and thus such current is lost to the load circuit (280 in FIG. 2).

Parasitic capacitances include parasitic gate-to-drain capacitance C_(gd) and parasitic gate-to-source capacitance C_(gs) of the active devices. By making the size of the DN FET used to implement the reservoir capacitor (370) large compared to the active devices, the capacitance of the reservoir capacitor (370) in each individual FWPump (100) is much larger than the parasitic capacitances of the active devices, thus lowering effect of the parasitic capacitances.

Additionally, it should be noted that the switching action of the active devices is an abrupt process. The abrupt process leads to a rapid charge transfer that gets pushed through the POS terminal (120) of each individual FWPump (100). The larger capacitance of the reservoir capacitor (370) tends to prevent the rapid charge transfers incurred by the switching action of the active devices. By smoothing out these rapid charge transfers, current sent to the load circuit (280 in FIG. 2) is more gradual, which generally leads to higher voltage output.

Furthermore, it should be noted that although an FWPump element (100) comprises an inverter stage and a voltage boosting stage, the first inverter (305) shown in FIGS. 3A and 3B may be utilized as the inverter stage for one or more FWPump elements. In an embodiment of the present disclosure, use of a single ring phase in the inverter ring, where a single ring phase comprises the various inverters (305, 315, 320, 325) in the inverter stage, to drive multiple DC capacitors (330, 335), full-wave bridge rectifiers (385), and reservoir capacitors (370) of the multiple voltage boosting stages allows for high ring pump output voltage. The high ring pump output voltage results from stacking of the DC capacitors (330, 335), full-wave bridge rectifier (385), and reservoir capacitor (370) of multiple voltage boosting stages that share the same inverter stage. In addition to the high ring pump output voltage, the ring pump may also run at higher frequencies due to effectiveness of filtering and charge delivery. Specifically, pulsed delivery of charge is integrated onto the reservoir capacitor (370) subsequent to filtering provided by the buffering and the DC isolation. This filtering reduces or removes an AC component of power pulses and aids in accumulation of DC energy.

In another embodiment, instead of utilizing a single ring phase to drive multiple voltage boosting stages, a first inverter (305) can be utilized to drive the various inverters (315, 320, 325) in multiple inverter stages as well as the DC capacitors (330, 335), full-wave bridge rectifier (385), and reservoir capacitor (370) of the multiple voltage boosting stages that share the same first inverter (305).

Voltage multiplication, performed by stacked DC capacitors (330, 335), full-wave bridge rectifiers (385), and reservoir capacitors (370) that share a first inverter (305) or a single ring phase, is a function of number of stacked DC capacitors (330, 335), full-wave bridge rectifiers (385), and reservoir capacitors (370). Current yielded by these stacked components (330, 335, 370, 385) is a function of number of transitions per unit time (frequency) of the ring pump, which is proportional to 1/N where N is the number of stages (to be specifically described in the following example).

By way of example, consider a seven-stage ring pump, where each stage drives three lineups of DC capacitors (330, 335), full-wave bridge rectifiers (385), and reservoir capacitors (370). In this case, a “stage” of the ring pump comprises the various inverters (305, 315, 320, 325) and the three lineups of DC capacitors (330, 335), full-wave bridge rectifiers (385), and reservoir capacitors (370). Output voltage delivered by this seven-stage ring pump will be nearly equal to output voltage delivered by a twenty-one stage ring pump, where each inverter stage in the twenty-one stage ring pump is associated with one voltage boosting stage. However, output current of the seven-stage ring pump will be nearly three times output current of the twenty-one stage ring pump due to the seven-stage ring pump having an oscillation frequency three times the oscillation frequency of the twenty-one stage ring pump. The seven-stage ring pump of this example generally generates more voltage ripple than the twenty-one stage ring pump as a result of charge delivery pulses being aggregated at three times a per-pulse charge delivery. The per-pulse charge delivery refers to the case where each lineup of DC capacitor pair (330, 335), full-wave bridge rectifier (385), and reservoir capacitor (370) has its own set of inverters (305, 315, 320, 325).

FIG. 4 shows another embodiment of a ring pump. In the particular embodiment shown in FIG. 4, the ring pump comprises twenty-nine individual FWPumps. The components and operation of the individual FWPump were previously described in detail with reference to FIGS. 1, 2, 3A, and 3B.

Aside from the number of stages in the ring pump, operation of the ring pumps in FIGS. 2 and 4 is generally the same. The inverter ring for the embodiment in FIG. 4 is as follows. The OUT terminal of a first FWPump (400) is connected to the IN terminal of a second FWPump (405) by a serial connection (410). Similar serial connections are made between the IN terminal and OUT terminal of adjacent FWPumps. To complete the inverter ring of the ring pump, the OUT terminal of a last FWPump (420) is connected to the first FWPump (400) by a serial connection (425).

The voltage boosting stages of the ring pump are as follows. An initial voltage V₀ (450) is applied to the NEG terminal of the first FWPump (400). The POS terminal of the first FWPump (400) is connected to the NEG terminal of the second FWPump (405) by a serial connection (415). Similar serial connections are made between the NEG terminal and the POS terminal of adjacent FWPumps. At the last FWPump (420), a ring pump output voltage V_(ring) (430) is applied to a load circuit (460). The load circuit (460) can comprise any combination of components and interconnections between these components and is not part of the ring pump itself. In FIG. 4, the load circuit (460) is a simple RC circuit.

A decrease in the ring pump output voltage V_(ring) (430) will result from charge drawn by the load circuit (460). By supplying charge to the load circuit (460), charge stored by a reservoir capacitor (not shown) of the last FWPump (420) decreases. Charge from reservoir capacitors (not shown) of preceding FWPumps flows toward the reservoir capacitor of the last FWPump (420) to charge up the reservoir capacitor of the last FWPump (420). The iterations through the inverter ring will drive the voltage boosting stage of each FWPump such that the pump output voltage V_(ring) (430) increases back toward the voltage at which the output V_(ring) (430) saturates.

Also, in the embodiment in FIG. 4, an external IN FET (435) is placed in parallel to each FWPump. The external IN FET (435) functions as a smoothing capacitor that further lowers the ripple of the voltage V_(POS) output from the voltage boosting stage of each FWPump. Additional size of the ring pump due to the presence of the external IN FETs (435) is deemed small enough to tolerate the addition.

In general, the output voltage V_(ring) (430) saturates at around V_(ring)≈V₀N×(V_(DD)−V_(SS)), where N is the number of stages in the ring pump. For the embodiment shown in FIG. 4, the ring pump has N=29 stages. Consider, as before, that V₀=0 V, V_(DD)=+2 V, and V_(SS)=−1 V, the output voltage would be V_(ring)≈87 V. An actual measurement of the output voltage V_(ring) (430) would generally be lower due to losses associated with each of the components of the ring pump. Addition of more stages in the ring pump would generally yield higher output ring pump voltage V_(ring) (430).

An output current I_(ring) (465) to the load circuit (460) is given by an equation I_(ring)=V_(ring)/R_(load)=2f_(osc)C₀(V_(DD)−V_(SS)), where R_(load) is an equivalent resistance of the load circuit (460), C₀ is a capacitance value of the first and second capacitors (330, 335), and f_(osc) is an oscillation frequency of the inverter ring. As with the output voltage V_(ring) (430), an actual measurement of the output current I_(ring) (465) would generally be lower than that calculated from the equation due to losses associated with each of the components of the ring pump.

As previously discussed and as observed from the equation, higher capacitances for the first and second capacitors (330, 335) yield higher output voltage V_(ring) (430) and current I_(ring) (465). Additionally, the equation shows a reason that oscillation frequency is generally kept at or near a constant value. Changes in the oscillation frequency f_(osc), which relates to changes in time between transition from a high voltage state to a low voltage state (or vice versa), causes changes in the output voltage V_(ring) (430) and current I_(ring) (465). Additionally, changes in the oscillation frequency f_(osc) causes changes in output voltage noise and power consumption of the ring pump, which lowers the output voltage V_(ring) (430) and current I_(ring) (465) of the ring pump. Voltage per stage, given by |V_(DD)−V_(SS)|, is generally independent of oscillation frequency. However, should cycle time (equivalently, inverse of the oscillation frequency) approach an RC time constant of the full-wave rectifier bridge (385) and the reservoir capacitor (370) (shown in FIGS. 3A and 3B), not all charge Q=C|V_(DD)−V_(SS)| would have transferred from the first and second capacitors (330, 335) to the full-wave rectifier bridge (385) and the reservoir capacitor (370) prior to reversal of voltage states.

FIG. 5 shows a top view of a circuit layout of an individual FWPump. FIG. 5 shows the various components shown in FIGS. 3A and 3B. Circuitry (500) on the left side of FIG. 5 contains the various inverters (305, 315, 320, 325) shown in FIGS. 3A and 3B. Using the same reference numerals as in FIGS. 3A and 3B for equivalent component components, FIG. 5 also shows the first and second capacitors (330, 335), the full-wave bridge rectifier (385), and the reservoir capacitor (370). The layout of the individual FWPump, as shown in FIG. 5, is used to implement each FWPump in the ring pump shown in FIG. 4. Voltage waveforms obtained from this ring pump, which include effects of parasitic elements, are shown in FIGS. 8C and 8D.

FIG. 6 shows input voltage for the inverter stage of the first FWPump (400) and the last FWPump (420) of the ring pump shown in FIG. 4. Specifically, a top voltage waveform (600) and a bottom voltage waveform (605) show the input voltages for the inverter stage of the first FWPump (400) and the last FWPump (420), respectively. As discussed earlier with reference to any one of FIGS. 1, 2, 3A, and 3B, the input voltage for the inverter stage of each FWPump is denoted by V_(IN) (125 in FIG. 1) and applied to the IN terminal (105 in FIG. 1) of each FWPump.

With reference back to FIG. 6, the input voltage for the inverter stage of each FWPump in the ring pump of FIG. 4 oscillates between a positive oscillator supply of V_(DD)=+2.5 V and a negative oscillator supply V_(SS)=0 V. In other words, the inverter stage of each FWpump is either in a high voltage state of +2.5 V or in a low voltage state of 0 V. As typical of a ring oscillator, at any given time instant, the first FWPump (400 in FIG. 4) and the last FWPump (420 in FIG. 4) are in opposite voltage states. For instance, at an arbitrary time instant A (610), the first FWpump (400 in FIG. 4) is transitioning from around 0 V to around +2.5 V while the last FWPump (420 in FIG. 4) is transitioning from around +2.5 V to around 0 V. Consequently, at a time instant a few nanoseconds after time instant A (610), the first FWPump (400 in FIG. 4) is at the high voltage state +2.5 V while the last FWPump (420 in FIG. 4) is at the low voltage state 0 V. For the waveforms (600, 605) shown in FIG. 6, oscillation frequency of the ring pump is around 75 MHz.

As seen in both voltage waveforms (600, 605), the high voltage state, low voltage state, and oscillation frequency stay substantially constant over time. As previously discussed, the first and second capacitors (330, 335), as shown in FIGS. 3A and 3B, contribute to the voltage states and oscillation frequency staying substantially constant over time by preventing coupling between voltages present in the voltage boosting stage of each FWPump and voltages present in the inverter stage of each FWPump.

FIG. 7 shows the output voltage V_(ring) (430) of the ring pump of FIG. 4 as a function of time under different load circuits (460) and different capacitance values for the first and second DC blocking capacitors (330, 335 in FIGS. 3A and 3B). The load circuit (460) shown in FIG. 4 and the input voltages shown in FIG. 6 are used to generate the output voltages. For the results shown in FIG. 7, the initial voltage V₀ (450) is set to +2.5 V.

A top curve (700) shows that without the load circuit (460) and with first and second capacitors (330, 335 in FIGS. 3A and 3B) of values C₀=C₁=200 fF in each FWPump, the ring pump embodiment shown in FIG. 4 has a ring output voltage V_(ring) (430) that saturates at about 65 V. A middle curve (705) shows that with a 10 MΩ resistor as part of the load circuit (460) and first and second capacitors (330, 335 in FIGS. 3A and 3B) of values C₀=C₁=200 fF in each FWPump, the voltage V_(ring) (430) saturates at around 60 V. Finally, a bottom curve (710) shows that with decreased capacitances for the first and second capacitors (330, 335) of C₀=C₁=84 fF in each FWPump, the voltage V_(ring) (430) saturates at below 50 V.

From the middle and bottom curves (705, 710), it is observed that higher capacitance values for the first and second capacitors (330, 335 in FIGS. 3A and 3B) yield higher values for the output voltage V_(ring) (430 in FIG. 4). As discussed earlier, DC blocking due to the first and second capacitors (330, 335 in FIGS. 3A and 3B) prevents coupling (improves isolation) between the inverter stage and the voltage boosting stage of each FWPump. Better prevention of coupling occurs with higher capacitance values for the first and second capacitors (330, 335 in FIGS. 3A and 3B). Such prevention of coupling aids in keeping oscillation frequency and voltage states (V_(DD) and V_(SS)) of the inverters nearly constant over time, which yields higher values for the output voltage V_(ring) (430 in FIG. 4) of the ring pump.

FIG. 8A shows voltage at the P node (340) and voltage at the Pb node (345), both nodes (340, 345) referred to in FIG. 3B, as a function of time for the embodiment depicted in FIG. 4. Specifically, FIG. 8A shows the voltages of the P node (340) and the Pb node (345) of the last FWPump (420) shown in FIG. 4. FIG. 8B shows the output voltage of the ring pump as a function of time. The ring pump output voltage V_(ring) (430) saturates at about 65 V.

An FWPump element shown in the layout in FIG. 5 is used to implement the ring pump in FIG. 4. Voltages at the P node (340 in FIG. 3B) and Pb node (345 in FIG. 3B) are shown in FIGS. 8C and 8D. Parasitic elements such as parasitic gate-to-drain capacitance C_(gd) and parasitic gate-to-source capacitance C_(gs) of the active devices are taken into effect in the voltages. FIG. 8C shows the voltage at the P node (340 in FIG. 3B) and Pb node (345 in FIG. 3B) of the last FWPump (420) shown in FIG. 4 that includes the parasitic effects. FIG. 8D shows the ring pump output voltage V_(ring) (430) of the ring pump of FIG. 4 as a function of time. By including the parasitic effects, the ring pump output voltage V_(ring) (430) saturates at a lower voltage of about 44 V.

As shown in FIGS. 8A and 8C, voltage level of the nodes P and Pb (340, 345 in FIG. 3B) is at a pedestal voltage given by the reservoir capacitor (370 in FIGS. 3A and 3B) of the last FWPump (420 in FIG. 4). In general, the first and second capacitors (330, 335 in FIGS. 3A and 3B), which function as DC capacitors, prevent coupling of the pedestal voltage with the inverters (305, 315, 320, 325 in FIGS. 3A and 3B) of any arbitrary FWPump. Consequently, as previously discussed, the first and second capacitors (330, 335 in FIGS. 3A and 3B) allow for the inverter stage of the FWPump to operate separately from the voltage boosting stage of the FWPump.

FIG. 9 shows a test chip that comprises an assortment of different embodiments of ring pumps. The different embodiments of the ring pump vary in number of stages in the ring pump and components used to implement the full-wave rectifier circuit. A 12 V positive pump (3) and a 12 V negative pump (4) comprised a fewer number of stages than the twenty-nine stages shown in FIG. 4. A 50 V HS pump (5), 50 V RS pump (6), and 50 V IS pump (7) are each twenty-nine stage ring pumps, where each pump (5, 6, 7) utilizes different types of MOS transistors to implement the full-wave bridge rectifier. Specifically, the HS pump (5) comprised HP and HN MOS transistors, RS pump (6) comprised RP and RN MOS transistors, and IS pump (7) comprised IP and IN MOS transistors. Note that ‘S’ in each of “HS”, “RS”, and “IS” refers to “synchronous” since each of the full-wave bridge rectifiers in these embodiments (5, 6, 7) are synchronous rectifiers. A 50 V I plain pump (8) used diode-connected IN-type MOS transistors and a 50 V PG plain pump (9) used diodes instead of MOS transistors to implement the full-wave bridge rectifier.

It should be noted that metal-metal-metal-poly (MMMP) plate (1) and MMMP edge (2) are test structures for high voltage plate capacitors included as part of the test chip along with the different embodiments of the ring pump.

FIG. 10 shows output voltages of the various ring pumps in FIG. 9 as a function of time. Reference numerals used in FIG. 10 correspond with those used in FIG. 9. For instance, the 12 V positive pump (3) in FIG. 9 has an output voltage given by an MPOS curve (3 a). The other ring pumps (4, 5, 6, 7, 8, 9) also have corresponding output voltages (4 a, 5 a, 6 a, 7 a, 8 a, 9 a). An enable signal is utilized for testing purposes, where the enable signal can be used to select only one of the various ring pumps (4, 5, 6, 7, 8, 9) at a time for testing.

FIG. 11 shows a test chip that implements a ring pump similar to the ring pump in FIG. 4. Specifically, the test chip shows a twenty-nine stage ring pump including twenty-eight FWPumps and one inverter (1130). The ring pump in FIG. 11 shows individual FWPump elements. In particular, a first FWPump element (1100), a last FWPump element (1105), and the inverter (1130) are identified. Operation of a cycle of an inverter ring in the ring pump begins at the inverter (1130) and circles back to the inverter (1130) via the last FWPump element (1105) on a right side of the test chip.

With reference to FIGS. 3A and 3B, the individual FWPump element (1100 in FIG. 11) comprises multiple inverters (305, 315, 320, 325), a first and second DC blocking capacitors (330, 335), a full-wave bridge rectifier (385), and a reservoir capacitor (370). The test chip in FIG. 11 shows the ring pump as well as the FWPump elements that form the ring pump. Specifically, a first and second column (1110) contain inverters (305, 315, 320, 325 in FIGS. 3A and 3B), a third and fourth column (1115) contain the first and second DC blocking capacitors (330, 335 in FIGS. 3A and 3B), a fifth and sixth column (1120) contain the full-wave bridge rectifiers (385 in FIGS. 3A and 3B), and a seventh and eighth column (1125) contain the reservoir capacitors (370 in FIGS. 3A and 3B) of each FWpump element.

FIGS. 12A-12C show graphs of output voltages of different embodiments of the ring pumps as a function of the output current. Specifically, FIGS. 12A, 12B, and 12C show graphs pertaining to data obtained from a 50 V ring pump that comprises a full-wave bridge rectifier implemented using RN MOS transistors, HN MOS transistors, and IN MOS transistors, respectively, under different values for a positive oscillator supply V_(DD) and where V_(SS)=0 V.

Each graph has a vertical line (1200) corresponding to a selected operating current for the 50 V ring pump. Type of MOS transistor and value for the positive oscillator supply V_(DD) can be selected based on required output voltage and/or required output current for a desired application.

The examples set forth above are provided to give those of ordinary skill in the art a complete disclosure and description of how to make and use the embodiments of the high voltage ring pump of the disclosure, and are not intended to limit the scope of what the inventor regards as his disclosure. Modifications of the above-described modes for carrying out the disclosure may be used by persons of skill in the art, and are intended to be within the scope of the following claims.

It is to be understood that the disclosure is not limited to particular methods or systems, which can, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used in this specification and the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the content clearly dictates otherwise. The term “plurality” includes two or more referents unless the content clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains.

A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, other embodiments are within the scope of the following claims. 

1. A circuital arrangement adapted to provide voltage to a load circuit, comprising a plurality of charge pumps, wherein each charge pump comprises an inverter stage and a voltage boosting stage, the circuital arrangement thus comprising: a plurality of inverter stages ring connected therebetween; and a plurality of voltage boosting stages serially connected therebetween.
 2. The circuital arrangement according to claim 1, wherein the plurality of charge pumps is an odd plurality of charge pumps.
 3. The circuital arrangement according to claim 1, wherein, in each charge pump, the inverter stage is either in a first voltage state or a second voltage state.
 4. The circuital arrangement according to claim 1, wherein, in each charge pump, the voltage boosting stage is a function of the inverter stage.
 5. The circuital arrangement according to claim 4, wherein the plurality of charge pumps is an odd plurality of charge pumps.
 6. The circuital arrangement according to claim 4, wherein the voltage boosting stage of each charge pump comprises: a full-wave bridge rectifier; and a charge storage device connected with the full-wave bridge rectifier.
 7. The circuital arrangement according to claim 4, wherein the voltage boosting stage of each charge pump comprises: a first capacitor, wherein an input to the first capacitor is a first function of the inverter stage; a second capacitor, wherein an input to the second capacitor is a second function of the inverter stage; a full-wave bridge rectifier comprising a first input node and a second input node, wherein an input at the first input node is a function of an output of the first capacitor and an input at the second input node is a function of an output of the second capacitor; and a charge storage device serially connected with the full-wave bridge rectifier.
 8. The circuital arrangement according to claim 7, wherein the output of the first capacitor and the output of the second capacitor are complementary to each other.
 9. The circuital arrangement according to claim 7, wherein, in each charge pump, the inverter stage is either in a first voltage state or in a second voltage state.
 10. The circuital arrangement according to claim 7, wherein the input to the first capacitor and the input to the second capacitor are different voltage states selected from two voltage states.
 11. The circuital arrangement according to claim 4, wherein the voltage boosting stage of each charge pump comprises: a first set of inverters comprising one inverter or a plurality of serially connected inverters, wherein an input to the first set of inverters is a first function of the inverter stage; a second set of inverters comprising one inverter or a plurality of serially connected inverters, wherein an input to the second set of inverters is a second function of the inverter stage; a first capacitor, wherein an input to the first capacitor is a function of an output of the first set of inverters; a second capacitor, wherein an input to the second capacitor is a function of an output of the second set of inverters; a full-wave bridge rectifier comprising a first input node and a second input node, wherein an input at the first input node is a function of an output of the first capacitor and an input at the second input node is a function of an output of the second capacitor; and a charge storage device serially connected with the full-wave bridge rectifier.
 12. The circuital arrangement according to claim 11, wherein the output of the first capacitor and the output of the second capacitor are complementary to each other.
 13. The circuital arrangement according to claim 11, wherein the output of the first set of inverters and the output of the second set of inverters are different voltage states selected from two voltage states.
 14. The circuital arrangement according to claim 11, wherein the first set of inverters is serially connected, to the inverter stage on one end and the first capacitor on another end and the second set of inverters is serially connected to the inverter stage on one end and the second capacitor on another end.
 15. A charge pump element, comprising: an initial inverter, wherein an input voltage to the initial inverter is inverted to obtain a complementary output voltage; at least one pump block, wherein an output voltage of a particular pump block in the at least one pump block is larger in magnitude than an input voltage to the particular pump block in the at least one pump block; and a driving circuit connected with the initial inverter on one end and the at least one pump block on another end, wherein the driving circuit generates a first voltage and a second voltage based on the input voltage to the initial inverter, and wherein each of the first and second voltages are adapted to be applied to the at least one pump block.
 16. The charge pump element according to claim 15, wherein the pump block comprises: a full-wave bridge rectifier; and a charge storage device connected with the full-wave bridge rectifier.
 17. The charge pump element according to claim 16, wherein the driving circuit comprises a first capacitor connected with the at least one pump block and a second capacitor connected with the at least one pump block.
 18. The charge pump element according to claim 17, wherein the driving circuit further comprises: an odd plurality of inverters serially connected therebetween, wherein the odd number of inverters is connected to the initial inverter on one end and the first capacitor on another end; and an even plurality of inverters serially connected therebetween, wherein the even number of inverters is connected to the initial inverter on one end and the second capacitor on another end.
 19. A circuital arrangement adapted to provide voltage to a load circuit, comprising a plurality of stages, wherein each stage comprises the charge pump element according to claim 15, and wherein: the initial inverter of a particular stage is serially connected to an initial inverter of a next stage and an initial inverter of a previous stage, an initial inverter of a last stage is serially connected to an initial inverter of a first stage, the at least one pump block of the particular stage is serially connected to a pump block of the next stage and a pump block of the previous stage, an initial voltage is adapted to be applied to a pump block of the first stage, and a pump block of the last stage is adapted to be connected to the load circuit.
 20. A circuital arrangement adapted to provide an output voltage to a load circuit, comprising: a plurality of inverter stages ring connected therebetween; and a plurality of voltage boosting stages serially connected therebetween, wherein: each voltage boosting stage is coupled with one inverter stage in the plurality of inverter stages, an output of a voltage boosting stage in the plurality of voltage boosting stages is higher in magnitude than an output of a previous voltage boosting stage in the plurality of voltage boosting stages, and a last voltage boosting stage in the plurality of voltage boosting stages is adapted to provide the output voltage to the load circuit.
 21. A method for boosting voltage, comprising: generating a first oscillating signal; generating a second oscillating signal complementary to the first oscillating signal; and accumulating voltage based on the first oscillating signal and the second oscillating signal.
 22. The method according to claim 21, wherein each of the first and second oscillating signals is either at a first voltage state or a second voltage state.
 23. The method according to claim 21, wherein the accumulating voltage is based on a difference between the first oscillating signal and the second oscillating signal. 